1. Field of the Invention
The present invention relates to an information processing apparatus, an information processing method and a computer program. To put it in detail, the present invention relates to an information processing apparatus for carrying out 3-dimensional graphic processing accompanying typically a 3DCG process and/or a CODEC process, relates to an information processing method to be adopted by the information processing apparatus and relates to a computer program implementing the information processing method.
2. Description of the Related Art
A 3DCG (3-Dimensional Computer Graphics) technology plays a role in displaying 3-dimensional data stored in a computer as a display easy to visually understand by carrying out a coordinate transformation process and a shading process on the data. Thus, the 3DCG technology can be used in a wide range of applications such as a video game and a user interface. In addition, the image CODEC processing includes a decompression process to decompress a compressed image stored in a computer and display an image obtained as a result of the decompression process as well as a compression process carried out inversely to the compression process to compress an image. The image CODEC processing is carried out in an apparatus such as a digital video camera, a digital still camera or a hand phone in order to display an image after decompressing the image or store an image in a memory after compressing the image.
In digital apparatus such as a video game, a digital still camera, a digital camera and a hand phone, the 3DCG processing and image CODEC processing are carried out frequently. FIG. 17 is a block diagram showing an example of hardware for carrying out the general 3DCG processing and the general image CODEC processing.
The typical hardware shown in FIG. 17 includes a CPU 11, a DSP 12, a RAM 13, a ROM 14, an external IF 15 and a media processing functional block 20 typically employing a JPEG processing functional block 21, a MPEG processing functional block 22 and a 3DCG processing functional block 23 in the case of the example shown in the figure. The JPEG processing functional block 21 is a section configured to carry out image CODEC processing according to JPEG whereas the MPEG processing functional block 22 is a section configured to carry out image CODEC processing according to MPEG. The 3DCG processing functional block 23 is a section configured to carry out a 3DCG function.
The JPEG processing functional block 21, the MPEG processing functional block 22 and the 3DCG processing functional block 23 each have a processing circuit dedicated to processing unique to the functional block. It is to be noted that the dedicated data processing functional blocks are each also referred to as a functional IP (Intellectual Property).
Instead of making use of such functional IPs (or dedicated data processing functional blocks), there is a technique referred to as a software processing technique by which software is executed by a general-purpose computer having a high processing speed. Since image drawing processing must be generally carried out in a real-time manner, however, the performance of a CPU employed in an ordinary digital apparatus is not high enough for executing the image drawing processing in a real-time manner. For this reason, a dedicated processing circuit is normally used for executing the image drawing processing in a real-time manner. In this case, however, all functional IPs (dedicated data processing functional blocks) must be employed in the dedicated processing circuit, raising a problem of an increased area of an LSI for implementing the functional IPs.
A demand made in past recent years as a demand for a high performance of each IP function is lower than the same demand made presently. Thus, even if a logic circuit was employed for each function in the dedicated processing module, there was no problem. However, there is now a demand for data processing to make the 3DCG technology abundant in image expressions. For example, by carrying out a shading process making use of a program referred to as a shader, it is possible to make the 3DCG technology abundant in image expressions. In a typical shading process adopting a shading technique based on the 3DCG technology, the brightness of each corner point of a plane is computed and the brightness of each point on the plane is then found by linear interpolation based on the computed brightness of each corner point. In addition, the 3DCG technology has been becoming advanced along with the rising demand for performance and functions. As for the image CODEC technology, its algorithm has been becoming complicated and diversified as indicated by the following progression:MPEG-2→MPEG-4→MPEG-4AVC/H.264
The configurations of the general processes based on the 3DCG and the CODEC technologies are explained by referring to FIGS. 18 and 19 respectively. 3DCG processing is explained by taking an OpenGl process, which is a typical API, as an example. The configuration shown in FIG. 18 as the configuration of the 3DCG processing is introduced in the following document: OpenGL, 2.0 Overview 2003 3Dlabs, Inc.
Vertex information stored in advance in a memory 31 as information on vertices of an object coordinate system is transferred to a vertex processor 32. The vertex processor 32 executes a program prepared in advance in order to carry out vertex processing on the vertex information. As a result of the vertex processing, the vertex processor 32 supplies output vertex information set in a clip coordinate system to a vertex-information processing execution unit 35. The vertex-information processing execution unit 35 outputs its result to a clip/project view cull process 36. The clip/project view cull process 36 is carried out on the result received from the vertex-information processing execution unit 35. The clip/project view cull process 36 outputs its result to a rasterize process 37.
Fragments output by the rasterize process 37 are supplied to a fragment processor 38 for carrying out a fragment process. Besides the fragment process, the fragment processor 38 may also carry out a variety of blend processes by using a texture read out from a texture memory 40. The fragment processor 38 outputs a result of the fragment process to a per fragment operation 39. The result of the per fragment operation 39 is supplied to a frame buffer 41. The result stored in the frame buffer 41 is then is subjected to a 1-frame process, a result of which is finally read out from the frame buffer 41 and displayed. It is to be noted that details of the 3DCG processing are described in a document describing the OpenGL 2.0 standard with a title of “The OpenGL Graphic System: A Specification.”
An image CODEC compression process is carried out in accordance with typically an image CODEC processing configuration shown in FIG. 19. An input image is subjected to an intra-frame prediction process. As an alternative, a result of a movement compensation process carried out on different frames is subtracted from the input image to give a difference which is then sequentially subjected to an orthogonal transform process, a quantization process and an entropy encoding process. The output of the quantization process is supplied to an inverse quantization process whereas the output of the inverse quantization process is supplied to an inverse orthogonal transform process. The output of the inverse orthogonal transform process is added to the result of the movement compensation process and the sum is filtered in a loop filtering process. An image frame of the loop filtering process is then stored in a frame memory. The movement compensation process is a movement prediction process carried out on an image stored in the frame memory. In addition, a vector output by the movement prediction process and the output of the intra-frame prediction process are also subjected to the entropy encoding process in the same way as the output of the quantization process. The result of the entropy encoding process is a stream.
CODEC decoding processing is basically process carried out in a sequence inverse to that of the CODEC encoding processing described above. However, the CODEC decoding processing does not include the movement prediction process and the inverse processes (that is, the inverse quantization process and the inverse orthogonal transform process).
As described above, FIG. 18 shows the configuration of the 3DCG processing whereas FIG. 19 shows the configuration of the image CODEC processing. In an ordinary configuration, each of the 3DCG and the image CODEC processing is carried out by an independent functional IP or a data processing functional block. To put it concretely, as described earlier by referring to FIG. 17, the JPEG processing functional block 21 is a section configured to carry out image CODEC processing according to JPEG whereas the MPEG processing functional block 22 is a section configured to carry out image CODEC processing according to MPEG. The 3DCG processing functional block 23 is a section configured to carry out the 3DCG processing.
In the case of the image CODEC processing supporting a plurality of standards, some circuits such as a movement detection circuit and a movement compensation circuit may be shared by the standards as circuits common to the standards. For every one of the standards, however, there are also a number of peculiar circuits. In addition, logic circuits of any other function such as the 3DCG circuit are not circuits that can be shared by the standards. Examples of functional IP (or each dedicated data processing functional block) of the image CODEC processing are the JPEG processing functional block 21 for carrying out image CODEC processing according to JPEG and the MPEG processing functional block 22 for carrying out image CODEC processing according to MPEG as shown in FIG. 17.
If each functional IP (or each dedicated data processing functional block) is employed in accordance with such a technique, the size of the circuit becomes large. In order to meet a demand for a high speed in every process and keep up with an increase of the amount of processed data, a gate is used for every implementing functional IP (or every dedicated data processing functional block) as a logic circuit. In this case, the size of the gate also increases. Thus, the area of an LSI mounted on the digital apparatus increases and, as a result, the manufacturing cost also rises faster. In addition, if the area of an LSI mounted on the digital apparatus put to practical use increases, there is raised a problem that the power consumptions of the LSI and the digital apparatus rise due to leak currents that flow even if a variety of functions are not being carried out.